
import uvm_pkg::*;

`include "uvm_macros.svh"

//   class eht_mac_tx_transaction extends uvm_sequence_item;
//         rand    bit [7:0]   axis_tx_data;
//         rand    bit         axis_tx_valid;
//         rand    bit         axis_tx_ready;
//         rand    bit         axis_tx_last;
//         rand    bit [31:0]  axis_tx_user;

//     //向工厂注册此类
//     `uvm_object_utils(eht_mac_tx_transaction)



//     endclass

class eht_mac_tx_driver extends uvm_driver;
    //virtual eht_mac_tx_intf intf;
    `uvm_component_utils(eht_mac_tx_driver)

    function new(string name = "eht_mac_tx_driver", uvm_component parent = null);
        super.new(name, parent);
        `uvm_info("eht_mac_tx_driver","new is called",UVM_LOW)
    endfunction

    task main_phase(uvm_phase phase);
        //object maismch,if there is not raise,the task finish immdately
        phase.raise_objection(this);
        tb_ethernet_mac_tx.axis_tx_data <= 0;
        tb_ethernet_mac_tx.axis_tx_valid <= 0;
        tb_ethernet_mac_tx.axis_tx_last <= 0;
        tb_ethernet_mac_tx.axis_tx_user <= 0;

        while(tb_ethernet_mac_tx.rst)
            @(posedge tb_ethernet_mac_tx.clk);
        
        tb_ethernet_mac_tx.axis_tx_user <= 32'h0020_8002;
        repeat(10) begin
            wait(tb_ethernet_mac_tx.axis_tx_ready==1);
            for(int i=0; i<32; i++) begin
                @(posedge tb_ethernet_mac_tx.clk);
                tb_ethernet_mac_tx.axis_tx_data <= i;
                tb_ethernet_mac_tx.axis_tx_valid <= 1;
                if(i==31)
                    tb_ethernet_mac_tx.axis_tx_last <= 1;
                `uvm_info("eht_mac_tx_driver","tx data is drived",UVM_LOW)
            end
            @(posedge tb_ethernet_mac_tx.clk);
            tb_ethernet_mac_tx.axis_tx_data <= 0;
            tb_ethernet_mac_tx.axis_tx_valid <= 0;
            tb_ethernet_mac_tx.axis_tx_last <= 0;
            @(posedge tb_ethernet_mac_tx.clk);

        end
        //when there is raise ,the simlation finshed when drop
        phase.drop_objection(this);
    endtask

endclass




module tb_ethernet_mac_tx;

    logic   clk             ;
    logic   rst             ;
    logic   [7:0]axis_tx_data    ; 
    logic   [31:0]axis_tx_user    ; 
    logic   axis_tx_last    ; 
    logic   axis_tx_valid   ; 
    logic   axis_tx_ready   ; 
    logic   [7:0]gmii_txdata     ; 
    logic   gmii_txvalid    ;    
  
    mac_tx dut_mac_tx(
        .i_clk                   ( clk          ),
        .i_rst                   ( rst          ), 
        .i_set_target_mac        ( 0            ),
        .i_set_target_valid      ( 0            ),
        .i_set_source_mac        ( 0            ),
        .i_set_source_valid      ( 0            ),
        .i_broadcast             ( 0            ),
        .i_axis_tx_data          ( axis_tx_data ),
        .i_axis_tx_user          ( axis_tx_user ),
        .i_axis_tx_last          ( axis_tx_last ),
        .i_axis_tx_valid         ( axis_tx_valid),
        .o_axis_tx_ready         ( axis_tx_ready),
        .o_gmii_txdata           ( gmii_txdata  ),
        .o_gmii_txvalid          ( gmii_txvalid )
    );

    initial begin
        clk <= 0;
        forever begin
            #4ns;
            clk <= ~clk;
        end
    end

    initial begin
        rst <= 1;
        #100ns;
        @(posedge clk)
        #1ns;
        rst <= 0;
    end

    initial begin
        run_test("eht_mac_tx_driver");
    end

endmodule